1. Field of the Invention
The present invention relates to computer systems using a bus bridge(s) to interface a central processor(s), video graphics processor(s), random access memory and input-output peripherals together, and more particularly, and more particularly, in utilizing a bus bridge(s) in a computer system for dual accelerated graphics ports.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened up many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers. These personal computers may be stand-alone workstations (high end individual personal computers), desk-top personal computers, portable lap-top computers and the like, or they may be linked together in a network by a xe2x80x9cnetwork serverxe2x80x9d which is also a personal computer which may have a few additional features specific to its purpose in the network. The network server may be used to store massive amounts of data, and may facilitate interaction of the individual workstations connected to the network for electronic mail (xe2x80x9cE-mailxe2x80x9d), document databases, video teleconferencing, white boarding, integrated enterprise calendar, virtual engineering design and the like. Multiple network servers may also be interconnected by local area networks (xe2x80x9cLANxe2x80x9d) and wide area networks (xe2x80x9cWANxe2x80x9d).
A significant part of the ever increasing popularity of the personal computer, besides its low cost relative to just a few years ago, is its ability to run sophisticated programs and perform many useful and new tasks. Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers (both workstation and network servers) has been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer system microprocessor central processing unit (xe2x80x9cCPUxe2x80x9d). The peripheral devices"" data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high speed expansion bus standard is called the xe2x80x9cPeripheral Component Interconnectxe2x80x9d or xe2x80x9cPCI.xe2x80x9d
Several official specifications and other documents relating to various aspects of the PCI Local Bus are currently available from the PCI Special Interest Group. Some examples of those documents include the PCI Local Bus Specification, revision 2.1; the PCI Local Bus Specification, revision 2.2 (PCI Conventional 2.2 Specification), the PCI-X 1.0a Specification, the Mini PCI Specification, the PCI/PCI Bridge Specification, revision 1.0; the PCI System Design Guide, revision 1.0; the PCI BIOS Specification, revision 2.1, the Small PCI 1.5s Specification, and the Engineering Change Notice (xe2x80x9cECNxe2x80x9d) entitled xe2x80x9cAddition of xe2x80x98New Capabilitiesxe2x80x99 Structure,xe2x80x9d dated May 20, 1996, the disclosures of which are hereby incorporated by reference. These PCI specifications and ECN are available from the PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214.
A computer system has a plurality of information (data and address) buses, such as a host bus, a memory bus, at least one high speed expansion local bus such as the PCI bus, and other peripheral buses such as the Small Computer System Interface (SCSI), Extension to Industry Standard Architecture (EISA), and Industry Standard Architecture (ISA). The microprocessor(s) of the computer system communicates with main memory and with the peripherals that make up the computer system over these various buses. The microprocessor(s) communicates to the main memory over a host bus to memory bus bridge. The peripherals, depending on their data transfer speed requirements, are connected to the various buses which are connected to the microprocessor host bus through bus bridges that detect required actions, arbitrate, and translate both data and addresses between the various buses.
Increasingly sophisticated microprocessors have revolutionized the role of the personal computer by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and mini-computer systems. Some representative examples of these new microprocessors are the xe2x80x9cPENTIUMxe2x80x9d, xe2x80x9cPENTIUM PROxe2x80x9d, xe2x80x9cPENTIUM IIxe2x80x9d, xe2x80x9cPENTIUM IIIxe2x80x9d and xe2x80x9cPENTIUM 4 (registered trademarks of Intel Corporation). Advanced microprocessors are also manufactured by Advanced Micro Devices, Cyrix, IBM, Digital Equipment Corp., and Motorola.
These sophisticated microprocessors have, in turn, made possible running complex application programs using advanced three dimensional (xe2x80x9c3-Dxe2x80x9d) graphics for computer aided drafting and manufacturing, engineering simulations, games and the like. Increasingly complex 3-D graphics require higher speed access to ever larger amounts of graphics data stored in memory. This memory may be part of the video graphics processor system, but, preferably, would be best (lowest cost) if part of the main computer system memory. Intel Corporation has proposed a low cost but improved 3-D graphics standard called the xe2x80x9cAccelerated Graphics Portxe2x80x9d (AGP) initiative. With AGP 3-D, graphics data, in particular textures, may be shifted out of the graphics controller local memory to computer system memory. The computer system memory is lower in cost than the graphics controller local memory and is more easily adapted for a multitude of other uses besides storing graphics data.
The Intel AGP 3-D graphics standard defines a high speed data pipeline, or xe2x80x9cAGP bus,xe2x80x9d between the graphics controller and system memory. This AGP bus has sufficient bandwidth for the graphics controller to retrieve textures from system memory without materially affecting computer system performance for other non-graphics operations. The Intel 3-D graphics standard is a specification which provides signal, protocol, electrical, and mechanical specifications for the AGP bus and devices attached thereto. This specification is entitled xe2x80x9cAccelerated Graphics Port Interface Specification Revision 1.0, xe2x80x9d dated Jul. 31, 1996, (xe2x80x9cAGP1.0xe2x80x9d) the disclosure of which is hereby incorporated by reference. Enhancements to the AGP1.0 Specification are included in the xe2x80x9cAccelerated Graphics Port Interface Specification Revision 2.0, xe2x80x9d dated May 4, 1998 (xe2x80x9cAGP2.0xe2x80x9d), the disclosure of which is hereby incorporated by reference. Both the AGP1.0 and AGP2.0 Specifications are available from Intel Corporation, Santa Clara, Calif.
The AGP1.0 interface specification uses the 66 MHz PCI (Revision 2.1) specification as an operational baseline, with three performance enhancements to the PCI specification which are used to optimize the AGP1.0 Specification for high performance 3-D graphics applications. These enhancements are: 1) pipelined memory read and write operations, 2) demultiplexing of address and data on the AGP bus by use of sideband signals, and 3) data transfer rates of 133 MHz for data throughput in excess of 500 megabytes per second (xe2x80x9cMB/sxe2x80x9d). The remaining AGP1.0 Specification does not modify the PCI specification, but rather provides a range of graphics-oriented performance enhancements for use by 3-D graphics hardware and software designers. The AGP1.0 Specification is neither meant to replace nor diminish full use of the PCI standard in the computer system. The AGP1.0 Specification creates an independent and additional high speed local bus for use by 3-D graphics devices such as a graphics controller, wherein the other input-output (xe2x80x9cI/Oxe2x80x9d) devices of the computer system may remain on any combination of the PCI, SCSI, EISA and ISA buses. The AGP1.0 Specification supports only 32-bit memory addressing. Further definition and enhancement of the AGP 1.0 Specification is more fully defined in xe2x80x9cCompaq""s Supplement to the xe2x80x98Accelerated Graphics Port Interface Specification Version 1.0xe2x80x99,xe2x80x9d Revision 0.8, dated Apr. 1, 1997, which is hereby incorporated by reference.
The AGP2.0 Specification supports 64-bit memory addressing, which is beneficial for addressing memory sizes allocated to the AGP device that are larger than 2 GB. The AGP2.0 Specification also includes several other enhancements. For example, the AGP2.0 Specification supports 1) 4xc3x97transfer mode with low (1.5V voltage electrical signals that allows four data transfers per 66 MHz clock cycle, providing data throughput of up to 1 GB/second; 2) five additional sideband signals; 3) a fast write protocol; 4) new input/output buffers; and 5) new mechanical connectors. The AGP 2.0 Specification is hereby incorporated by reference herein, and is attached hereto as Appendix A.
A draft version of the AGP 8xc3x97Specification (AGP Specification 3.0, Draft Version 0.95) was promulgated by Intel in May, 2001. The AGP3.0 data bus introduces AGP 8xc3x97transfer mode, which provides a peak theoretical bandwidth of 2.1 GB/s (32 bits per transfer at 533 MT/s). Both the common clock and source synchronous data strobe operation and protocols are similar to those employed by AGP2.0 with all modifications guided by the need to support the 8xc3x97data transfer rate of AGP3.0""s source synchronous mode. The AGP 3.0 Specification, Draft Version 0.95, is hereby incorporated by reference herein, and is attached hereto as Appendix B.
Regardless of the version of the AGP specification, to functionally enable the AGP 3-D graphics bus, new computer system hardware and software are required. This requires new computer system core logic designed to function as a host bus/memory bus/PCI bus to AGP bus bridge meeting the AGP1.0 or AGP2.0 Specifications, and new Read Only Memory Basic Input Output System (xe2x80x9cROM BIOSxe2x80x9d) and Application Programming Interface (xe2x80x9cAPIxe2x80x9d) software to make the AGP dependent hardware functional in the computer system. The computer system core logic must still meet the PCI and/or PCI-X standards referenced above and facilitate interfacing the PCI bus(es) to the remainder of the computer system. In addition, new AGP compatible device cards must be designed to properly interface, mechanically and electrically, with the AGP bus connector.
AGP and PCI device cards are not physically or electrically interchangeable even though there is some commonality of signal functions between the AGP and PCI interface specifications. The AGP specifications only make allowance for a single AGP device on an AGP bus. Whereas the PCI specification allows two PCI devices on a PCI bus running at 66 MHz. The single AGP device is capable of functioning in a 1xc3x97mode (264 MB/s peak), a 2xc3x97mode (532 MB/s peak), a 4xc3x97mode (1 GB/s peak) or an 8xc3x97mode (theoretical limit of 2.1 GB/s peak). The AGP bus is defined as a 32 bit bus, or four bytes per data transfer. The PCI bus is defined as either a 32 bit or 64 bit bus, or four or eight bytes per data transfer, respectively. The AGP bus, however, has additional sideband signals which enable it to transfer blocks of data more efficiently than is possible using a PCI bus.
The purpose of the original AGP bus and the extensions set forth in subsequent versions of the specification is to provide sufficient video data throughput to allow increasingly complex 3-D graphics applications, particularly games, to run on personal computers. Some personal computer uses do not require high end 3-D graphics, but would greatly benefit from having an additional AGP card slot for accepting an additional input-output device such as another video graphics card (dual head monitors), a high speed network interface card (xe2x80x9cNICxe2x80x9d), a SCSI adapter, a wide area network digital router, and the like. Since the AGP specification is comprised of a superset of the 66 MHz, 32 bit PCI specification, a PCI device may also function on the AGP bus (different card slot connectors for the AGP and PCI device cards would be necessary). Thus, embedded (directly connected to the computer system motherboard) or card slot pluggable AGP and PCI devices could share the same AGP/PCI bus, controller and arbiter of a core logic chip set used in a computer system.
What is needed is an apparatus, method, and system for a personal computer that provides a core logic chip set having an AGP interface connected to an AGP bus and being capable of accommodating an additional AGP or PCI device on the AGP bus.
The present invention provides a core logic chip set that is capable of being a bridge between an AGP bus and host and memory buses wherein two AGP devices, or an AGP device and a PCI device may be connected to the AGP bus. An AGP bus having provisions for the AGP and PCI interface signals is connected to the core logic chip set and is adapted for connection to either two AGP devices or an AGP device and a PCI device. The core logic chip set of the present invention uses one of its arbiters for the two AGP devices or the AGP device and the PCI device on the AGP bus, and has Request (xe2x80x9cREQxe2x80x9d) and Grant (xe2x80x9cGNTxe2x80x9d) signal lines for each one of the devices connected to the AGP bus.
Two AGP devices, or one AGP device and one PCI device may be embedded on the computer system motherboard, or either or both devices may be on a separate card(s) which plugs into a corresponding card edge connector(s) attached to the system motherboard and connected to the AGP bus. The embodiments of the present invention contemplate a core logic chip set which may be one or more integrated circuit devices such as an Application Specific Integrated Circuit (xe2x80x9cASICxe2x80x9d), Programmable Logic Array (xe2x80x9cPLAxe2x80x9d) and the like.
The core logic chip set is connected to an AGP bus and provides for two AGP devices, or one AGP device and one PCI device connected to the AGP bus. Separate request (REQ#) and grant (GNT#) lines are provided for each device on the AGP bus. The AGP bus transfers data in the AGP 1xc3x97mode or PCI mode at up to 264 MB/s peak, depending upon whether an AGP device or PCI device, respectively, is the active device on the AGP bus. The present invention also contemplates two AGP devices in the 2xc3x97mode transferring data at up to 532 MB/s peak on the AGP bus, two AGP devices in the 4xc3x97mode transferring data at up to 1 GB/s peak or two AGP devices in the 8xc3x97mode transferring data at up to 2.1 GB/s peak.
An embodiment of the present invention utilizes a common bus for address, data and some control signals for both AGP and PCI devices. Separate xe2x80x9cSideband Address Portxe2x80x9d (xe2x80x9cSBA[7::0]xe2x80x9d) signal buses and xe2x80x9cRead Buffer Fullxe2x80x9d (xe2x80x9cRBF#xe2x80x9d) signal lines may be provided for each AGP device and are separate and distinct from the common bus. In this embodiment a PCI device may function as a 32 bit address and data width device running at a clock frequency of 66 MHz, as more fully defined in the PCI 2.1 Specification and the PCI 2.2 Specification, which are both incorporated by reference above. Separate Sideband Address Port (SBA[7::0]) signals for each AGP device enable concurrent pipelined data requests by allowing address information cycles to occur separate from the common 32 bit data bus (xe2x80x9cAD[31::0]xe2x80x9d), as more fully defined in the AGP Specification incorporated by reference. The AGP device(s) may also use PIPE addressing which uses the common data bus (AD[31::0]) for asserting address information. The PCI device must always use the AD[31::0] bus for addressing information.
Another embodiment of the present invention utilizes a separate bus for each AGP device (32 bit address and data width) and can utilize these separate buses as one bus for a 64 bit PCI device. In addition, a plurality of AGP buses are contemplated herein for the core logic chip set of the present invention. Multiples of two independent AGP buses also allow a plurality of 64 bit PCI devices to be accommodated with the present invention.
A bus switch in the core logic chip set combines the separate AGP buses into one PCI bus during computer system configuration or during Power On Self Test (xe2x80x9cPOSTxe2x80x9d) so that each device in the computer system (AGP or PCI) may be determined. When the computer system is first powered on and POST begins, the startup configuration software must scan the PCI bus or buses to determine what PCI or AGP devices exist and what configuration requirements they may have. This process is commonly referred to as enumerating, scanning, walking or probing the bus. It may also be referred to as the discovery process. The software program which performs the discovery process may be referred to as the PCI bus enumerator. Both AGP and PCI device enumeration is done via PCI bus transactions.
During this discovery process, the AGP device registers are accessed using PCI bus cycles through a host/PCI bridge or PCI/PCI bridge. Each device has a different xe2x80x9cdevice numberxe2x80x9d as more fully defined in the PCI 2.2 Specification. A first AGP device would typically be hardwired as bus device number 0, having its IDSEL connected to AD16 of the AD[31::0] bus. A second AGP device would typically be hardwired as bus device number 1, having its IDSEL connected to AD17 of the AD[31::0] bus. The PCI device could be any bus device number 1-15 connected to AD17-31 (one only), respectively. The appropriate IDSEL lines may then be used to access the configuration registers of the AGP and PCI devices so as to read the capabilities of each device and its system requirements. Once information for all of the bus devices is determined, the core logic may be configured to the desired combination of either two AGP devices, or an AGP device and a PCI device.
The AGP transfer speed (AGP mode 1xc3x97, 2xc3x97, 4xc3x97 or 8xc3x97) is not configured during POST. The AGP mode may be configured with an Application Programming Interface (xe2x80x9cAPIxe2x80x9d) software of the operating system software. In the present invention, however, the computer system POST software may configure the AGP Status Register of the core logic chip set whose address is defined in the Capabilities Pointer (offset 34h) bits 7:0, the byte offset stored therein is hereinafter referred to as xe2x80x9cCAP_PTR.xe2x80x9d
The AGP devices use the PCI xe2x80x9cNew Capabilitiesxe2x80x9d structure, as more fully defined in the PCI 2.1 Specification ECR, incorporated by reference above, to implement a linked list of registers containing information for each function supported by the device. The xe2x80x9cNew Capabilitiesxe2x80x9d ECR is included in the PCI 2.2 Specification, which is incorporated by reference above. AGP status and command registers are included in the linked list of registers. In the AGP status register (offset CAP_PTR+4) the RATE field indicates the data transfer rates supported by the device. In the AGP command register (offset CAP_PTR+8) one bit in the DATA_RATE field is set to indicate the desired data transfer rate. Both AGP master and target devices must have the same bit set in the respective DATA_RATE fields, i.e., both AGP master and target must be capable of transferring data at the same rate, either 1xc3x97, 2xc3x97, 4xc3x97 or 8xc3x97.
The present invention contemplates running AGP devices in either the 1xc3x97, 2xc3x97, 4xc3x97 or 8xc3x97mode. API software sets the AGP master and target devices to operate at a common compatible AGP mode. Thus the core logic chip set RATE bits in the AGP status register (offset CAP_PTR+4) may force the API software to configure the AGP master device cards to the 1xc3x97mode if the core logic chip set indicates to the API software that only 1xc3x97mode is available. If the core logic indicates to the API software that it is capable of AGP 2xc3x97, 4xc3x97 or 8xc3x97modes, then the AGP master device(s) may be configured to run in one of those modes. This is true for all AGP devices since only one AGP command register is defined in the AGP specification.
The AGP Status Register (CAP_PTR+4) xe2x80x9cRATE fieldxe2x80x9d (bits 1:0) define the data transfer rates (mode 1xc3x97, 2xc3x97, 4xc3x97 or 8xc3x97) supported by the associated AGP device, i.e., the core logic chip set and AGP master(s). When two AGP devices are detected, or when one AGP device and one PCI device are detected during POST, the Rate field in the AGP Status Register of the core logic chip set may be configured by the POST software to indicate that only AGP 1xc3x97mode is available. If only one AGP device and no PCI device is detected, then the Rate field may be configured by the POST software to indicate that an AGP 2xc3x97 mode, 4xc3x97 mode or 8xc3x97mode is available. It is contemplated in the present invention that the Rate field in the AGP Status Register may be configured through a xe2x80x9cback doorxe2x80x9d hardware register of the computer system that is accessible by the startup software in the ROM BIOS. The Rate field being set by the back door register after POST determines whether the AGP 8xc3x97, 4xc3x97, 2xc3x97 or 1xc3x97 mode is appropriate. The API software may then read the RATE field in the Status register of the core logic chip set and will then configure the DATA_RATE field in the AGP command register (offset CAP_PTR+8) of each AGP master device for the AGP mode (1xc3x97, 2xc3x97, 4xc3x97 or 8xc3x97) previously programmed after POST.
In the AGP 2xc3x97 mode, 8 bytes of data are transferred during each single clock (xe2x80x9cCLKxe2x80x9d) cycle. The AD[31::0] bus is 32 bits or 4 bytes wide, thus, two 4 byte data transfers must be made during each CLK cycle. This is accomplished in the AGP 2xc3x97 mode by using additional source synchronous strobes derived from the AGP clock (CLK). These strobe signals are: AD_STB0 and AD_STB1 which indicate when valid data is present on AD[31::0], and SB_STB which is used in conjunction with the SBA[7::0] signals. These strobe signals allow an effective data transfer rate of eight (8) bytes of data per AGP CLK (66 MHz). In the present invention, separate strobe signals may be used between each AGP connector and the core logic chipset so as not to excessively load down the strobe signals.
AGP 2.0 4xc3x97 data transfers are similar to 2xc3x97 transfers except an entire 16 bytes can be transferred during a single CLK period. This requires that four 4 byte pieces of data are transferred across the AD bus per CLK period. First a read data transfer will be discussed, and then a write transfer. The control signals are identical as for the 2xc3x97read, except that AD_STBx# has been added when data is transferred at 16 bytes per CLK period. AD_STBx# represents the compliment of AD_STB0 and AD_STB1 and are used with AD_STB0 and AD_STB1 by the 4xc3x97interface logic to know when valid data is present on the AD bus. The receiving agent has two choices of how it uses the four strobes to latch data.
The first choice is to use only the falling edge of each strobe to latch data. The first falling edge of AD_STB0 is used to determine when the receiving agent latches the first four bytes of data residing on the AD bus, and the first falling edge of AD_STB0# is used to latch the second 4 bytes of the transaction. The second falling edge of AD_STB0 is used to determine when the receiving agent latches the third four bytes of data residing on the AD bus, and the second falling edge of AD_STB0# is used to latch the fourth 4 bytes of the transaction. Note that the rising edges of AD_STBx or AD_STBx# are never used to latch data when in the 4xc3x97transfer mode.
The second choice is to use the strobes as differential pairs and not as four separate signals. The compliment pairs are AD_STB0 and AD_STB0#; and AD_STB1 and AD_STB1#. When this choice is used, an internal latch signal is created in which data is latched on both the falling and rising edges. Assume for illustration purposes that the internal signal is AD_STBx in FIG. 6A. The first falling edge of AD_STBx is used to determine when the receiving agent latches the first 4 bytes of data residing on the AD bus and the first rising edge of AD_STBx is used to latch the second 4 bytes of the transaction. The second falling edge of AD_STBx is used to determine when the receiving agent latches the third 4 bytes of data residing on the AD bus and the second rising edge of AD_STBx is used to latch the fourth 4 bytes of the transaction. Note that the rising edges of the internal signal are used to latch data when in the 4xc3x97transfer mode.
The AGP 3.0 Specification introduces the 8xc3x97transfer mode, which is implemented in part using the signals AD_STBF[1:0], AD_STBS[1:0], DBI_HI and DBI_LO. The details of how those signals are implemented are set forth in the AGP 3.0 Specification, which is incorporated by reference above.
A PCI device may be recognized by its register configuration during system configuration or POST, and the speed of operation of the PCI device may be determined during POST by reading the 66 MHz-CAPABLE bit in the status register, and/or by a hardwired electrical signal xe2x80x9cM66ENxe2x80x9d as an active xe2x80x9chighxe2x80x9d input to the 66 MHz PCI device card. If any of the PCI devices on the PCI bus are not 66 MHz capable then the non-66 MHz capable PCI card will deactivate the M66EN signal pin by pulling it to ground reference. If all PCI devices on the PCI bus are 66 MHz capable then M66EN remains active high and each 66 MHz capable PCI card will operate at a 66 MHz bus speed.
The PCI 2.2 Specification supports a high 32 bit bus, referred to as the 64 bit extension to the standard low 32 bit bus. The 64 bit bus provides additional data bandwidth for PCI devices that require it. The high 32 bit extension for 64 bit PCI devices requires an additional 39 signal pins: REQ64#, ACK64#, AD[63::32], C/BE[7::4]#, and PAR64. These signals are defined more fully in the PCI 2.1 Specification incorporated hereinabove. 32 bit PCI devices work unmodified with 64 bit PCI devices. A 64 bit PCI device must default to 32 bit operation unless a 64 bit transaction is negotiated. 64 bit transactions on the PCI bus are dynamically negotiated (once per transaction) between the master and target PCI devices. This is accomplished by the master asserting REQ64# and the target responding to the asserted REQ64# by asserting ACK64#. Once a 64 bit transaction is negotiated, it holds until the end of the transaction. The REQ64# and ACK64# signals are externally held to a deasserted state by pull up resistors to ensure proper behavior when mixing 32 bit and 64 bit data width PCI devices on the PCI bus. A central resource controls the state of REQ64# to inform the 64 bit data width PCI device that it is connected to a 64 bit data width bus. If REQ64# is deasserted when RST# is deasserted, the PCI device is not connected to a 64-bit data width bus. If REQ64# is asserted when RST# is deasserted, the PCI device is connected to a 64 bit data width bus.
In the present invention, the AGP slot number 0 would be the first AGP slot to install an AGP compliant device card. Either AGP slot number 1 or PCI slot number 1 would receive the second AGP or PCI device, respectively. The first AGP slot number 0 would always have sideband addressing SBA[7::0] signals functionally connected to the core logic chip set. The second AGP slot number 1 could have the sideband addressing signals connected or not. A preferred embodiment of the present invention uses sideband addressing for both AGP devices. However, if no sideband addressing signals are connected to the AGP slot number 1, then the AGP device plugged into slot number 1 may use PIPE addressing exclusively (except in 8xc3x97mode, for which PIPE addressing is not supported). Both AGP devices could potentially use PIPE addressing instead of one using sideband addressing and the other using PIPE addressing. Sideband addressing must be used for both devices if support for 8xc3x97transfer mode is desired. Transferring data using AGP modes 1xc3x97, 2xc3x97, 4xc3x97 or 8xc3x97is contemplated in the present invention as disclosed above.
Since sideband addressing (SBA[7::0]) may be concurrent with data transfers on the AGP bus (AD[31::0]), separate address and data queues in the core logic chip set are contemplated for each AGP device. During data transfers, the appropriate AGP device is selected by its respective GNT# signal from the core logic chip set. Data is returned to the requesting AGP device in the order of the previously asserted addresses.
In another embodiment, a PCI device card connector may be placed proximate to an AGP device card connector on the computer system motherboard, and both PCI and AGP connectors may be connected to the AGP bus as logical slot 1 (REQ1# and GNT1#). It is contemplated in the present invention that either an AGP device card or a PCI device card, but not both, may be plugged into connector (AGP or PCI, respectively) slot 1. The PCI device plugged into the PCI slot number 1 connector would use the FRAME# signal instead of the PIPE# signal.
In the embodiment having two separate AGP buses, one for each AGP card slot, a 64 bit PCI device may be accommodated by using the address and data lines of the bus to the AGP slot number 0 for the AD[31::0] signals and the address and data lines of the bus to the AGP slot number 1 for the AD[63::32] signals. The AGP device in slot number 0 would maintain its data transaction operations on the AD[31::0] bus using either sideband addressing or PIPE addressing. PIPE addressing is not supported by the AGP 3.0 Specification, so PIPE addressing may not be used if AGP 8xc3x97transfer mode is desired.
The PCI device would operate as a 64 bit device by using both of the AGP buses for the AD[63::0] signals. Registered PCI (xe2x80x9cRegPCIxe2x80x9d) is also contemplated herein for the present invention, as more fully described in commonly owned U.S. Pat. No. 6,067,590, issued on May 23, 2000, entitled xe2x80x9cData Bus Agent Including a Storage Medium Between a Data Bus and the Bus Agent Devicexe2x80x9d by Dwight Riley and Christopher J. Pettey; and U.S. Pat. No. 5,937,173, issued on Aug. 10, 1999, entitled xe2x80x9cDual Purpose Computer Bridge Interface for Accelerated Graphics Port or Registered Peripheral Component Interconnect Devicesxe2x80x9d by Sompong Olarig, Dwight Riley and Ronald T. Horan. Both of these patent applications are hereby incorporated by reference.
It is contemplated that AGP and PCI devices such as video controllers capable of driving dual headed monitors, SCSI arrays, high speed network interface cards, asynchronous transfer mode (xe2x80x9cATMxe2x80x9d) routers and the like, may be used with the dual AGP apparatus, method and system of the present invention. Memory coherency of PCI transactions could be accomplished in accordance with Revision 2.2 of the PCI Local Bus Specification.
Other features and advantages will be apparent from the following description of presently preferred embodiments of the invention, given for the purpose of disclosure and taken in conjunction with the accompanying drawings.